1. Field of the Invention
The present invention relates to protection of a load driving and diagnosis system that feeds a current to a connected load so as to drive the load, and a diagnosis method implemented in the system.
2. Description of the Related Art
Many loads are mounted in a vehicle, and switches formed with semiconductors are used to control conductions of the loads. The semiconductor switches are generally adopted because they contribute to a reduction in a price or a weight. For a further reduction in the price, a control device having a semiconductor switch and a drive circuit, which drives the semiconductor switch, integrated thereinto is often employed in the form of an integrated circuit. Referring to FIG. 15, the control device will be described below.
In FIG. 15, there are shown a CPU control means 1 that controls the timing of energizing or de-energizing a load, a load drive command 2, an input command terminal 3 of an integrated circuit 31, an input buffer 4, an internal command signal 5, a driver drive/shutoff means 6 that drives or shuts off a driver, a drive/shutoff control signal 7, a driver means 8 that drives a semiconductor switch, a high-side driver 8a, a low-side driver 8b, a gate driving sink current 10 to be produced by the high-side driver 8a, and a gate driving source current 11 to be produced by the low-side driver 8b. 
Reference numeral 12 is a gate signal with which the semiconductor switch is directly controlled. Reference numeral 13 is a semiconductor switching circuit that is the semiconductor switch, and reference numeral 13a is a parasitic diode, 13b is a gate input parasitic capacitor of the semiconductor switching circuit. Reference numeral 29 is a switching circuit output voltage of the semiconductor switching circuit 13 which is outputted to outside through an output terminal 30.
Reference numeral 16 is a switching circuit input current that flows through the semiconductor switching circuit 13. Reference numeral 17 is a shunt resistor for current detection. An overcurrent detection means 22 detects an overcurrent condition according to a potential difference 21 between voltages 19 and 20 at the terminals of the shunt resistor. Reference numeral 23 is an overcurrent detection signal. Reference numeral 24 is a break condition holding means that when an overcurrent condition is established, sustains a break condition for a predetermined time that starts at the timing at which the overcurrent detection signal 23 is outputted. Reference numeral 25 is a break condition holding signal that is inputted to the driver drive/shutoff means 6. The semiconductor switching circuit 13 is broken in response to an output signal of the driver drive/shutoff means 6.
Reference numeral 26 is a diagnostic output means that outputs diagnostic information to the CPU control means 1, inputs the overcurrent detection signal 23, and outputs a diagnostic output signal 28 according to a CPU readout control signal 32. Reference numeral 27 is a diagnostic output terminal, and reference numeral 33 is a readout control signal input terminal. Reference numeral 49 is a voltage holding means. When a switch output voltage 29 reaches a predetermined voltage, the voltage holding means 49 turn on the semiconductor switching circuit 13 to sustain the predetermined voltage. Reference numeral 100 is a ground, and reference numeral 101 is a power supply. Moreover, reference numeral 31 is a semiconductor integrated circuit having the control device integrated on a chip.
Moreover, the diagnostic output means 26 of the semiconductor integrated circuit has a constitution shown in FIG. 16. In FIG. 16, there are shown an output circuit 26a that outputs diagnostic information according to the CPU readout control signal 32, an state transition means 26b that makes a state transition for overcurrent detection and diagnosis according to the overcurrent detection output signal 23. Reference numeral 61 is an overcurrent diagnostic output signal signifying that an overcurrent diagnostic state is set up.
The semiconductor integrated circuit 31 is generally used while being connected to an external load in a constitution shown in FIG. 17. In FIG. 17, there are shown a terminal capacitor 43 included for protecting the semiconductor integrated circuit from noises including a surge, and a wire harness 40 which is coupled to the switch output terminal 30 and to which a load 42 is coupled. Reference numeral 41 is a parasitic inductor of the wire harness 40. Reference numeral 45 is a reverse current that flows from the semiconductor integrated circuit 31 to the power supply due to a counter-electromotive force.
In the constitution, when a short circuit 44 to the power supply 101 of the load occurs accidentally, a current flows from the power supply 101 directly to the switch output terminal 30. A break is carried out in order to protect the semiconductor switching circuit 13.
In relation to the foregoing constitution, actions of respective circuits will be described in conjunction with the timing chart of FIG. 18 and the state transition chart of FIG. 19. In FIG. 18, reference numeral 60 is a period during which the power supply 101 of the load 42 is short-circuited. Reference numeral 61 is a transitional state of the state transition means 26b. The other reference numerals denote the same components as those shown in FIG. 15.
The load drive command 2 is inputted from the CPU control means. The semiconductor switching circuit 13 is turned on at timing A. The input current 16 flows into the semiconductor switching circuit 13, and the output terminal voltage 29 is driven low at the same time. Thereafter, if the power-supply short circuit 60 occurs at timing B, since current limiting by the load 42 is invalidated, the input current 16 increases. When the current value reaches a predetermined threshold (16a) at timing C, the voltage 21 across the terminals of the shunt resistor 17 for current detection, that is, the potential difference 21 between the terminals thereof increases and exceeds a predetermined threshold. Consequently, the overcurrent detection signal 23 is outputted.
The overcurrent detection signal 23 is inputted to the break condition holding means 24. Accordingly, the overcurrent break holding signal 25 is outputted and inputted to the driver drive/shutoff means 6. The drive/shutoff control signal 7 is driven high at timing D. Consequently, the sink current 11 flows into the driver means 8, and the gate signal 12 is driven low. Eventually, the semiconductor switching circuit 13 is turned off (broken).
At this time, a counter-electromotive force is developed in the parasitic inductor 41 of the wire harness 40 because of the break of the semiconductor switching circuit 13. A surge 29a occurs in the switching circuit output voltage 29. Since the voltage holding means 49 is added to the output stage of the semiconductor switching circuit, the surge 29a is held at a voltage level 29b. Since the terminal capacitor 43 is externally added to the switch output terminal 30, the capacitor is charged with the voltage of the voltage level 29b at which the surge is held.
When the load is normally energized or de-energized, the voltage level 29b is usually set to a voltage higher than the supply voltage level in order to quickly block a load current. Consequently, when a break occurs under an overcurrent condition as mentioned above, the voltage level 29b gets higher than the supply voltage 101. The reverse current 45 therefore flows from the terminal capacitor 43, which is charged at the voltage level 29b, to the power supply 101.
The current flows through the parasitic inductor 41. Even after the terminal capacitor 43 is discharged, the current attempts to keep flowing, and attracts a current from the switching circuit output terminal 30. Consequently, the switching circuit input current becomes a negative current 16b, and a current is attracted from the output terminal 30. At the same time, the switching circuit output voltage 29 drops to be a negative voltage.
The instant that a break occurs at timing D, an LC oscillation arises between the terminal capacitor 43 and parasitic inductor 41. Consequently, a negative current flows into the switching circuit output terminal 30. Eventually, a phenomenon in which the switching circuit output voltage 29 drops to be negative takes place.
According to the conventional technology, as described in Patent Document 1, when a break occurs after an overcurrent is detected, the sink current 11 of the semiconductor switch driver means 8 is controlled in order to alleviate the adverse effect of the phenomenon. Since a semiconductor switching circuit exists as a unit in a semiconductor switching device such as an insulated-gate bipolar transistor (IGBT) employed in the related art, a large current can flow into the circuit. Therefore, the sink current 11 is controlled in order to gradually decrease a switch break speed. Since the break speed thus gets lower, any problem is not posed by the counter-electromotive force.
The patent document 1: JP-A-04-172962.
However, when the semiconductor switching circuit 13 is broken, if the negative current like the one 16b flows, the constitution including the semiconductor integrated circuit 31 may be gravely damaged. The semiconductor switching circuit 13 is normally formed with an n-channel MOS, and is generally accompanied by a parasitic diode 13a. 
The negative current flows through the parasitic diode 13a. This causes the potential at the n-type layer on the semiconductor integrated circuit to drop to be negative. Consequently, another parasitic element may be generated and a malfunction of a circuit maybe invited. Moreover, a latch-up that is a large-current inflow phenomenon occurs due to conduction of a parasitic transistor, though it depends on a temperature requirement or a layout requirement for the semiconductor integrated circuit. Eventually, the semiconductor integrated circuit may be thermally destroyed or any other serious problem may arise.
The above phenomenon can be prevented by excluding the terminal capacitor 43 or diminishing the capacitance. However, the durability against an externally applied surge may be degraded, and surge destruction may occur. Moreover, even when an optimal capacitance is selected for the terminal capacitor for fear an LC oscillation may occur, since the requirement for the parasitic inductor 41 varies depending on the length of the external harness 40 or the like, it is very hard to determine the capacitance of the terminal capacitor which meets every requirement.
In the constitution having the semiconductor switching circuit included in the semiconductor integrated circuit, many circuits are integrated on the same silicon substrate. Moreover, the semiconductor switching circuit 13 is designed to occupy a minimum necessary area for the purpose of decreasing an entire area. If a large current keeps flowing for a long period of time, the semiconductor switching circuit would be destroyed due to heat dissipation. In other words, there is difficulty in selecting an optimal gradient in a breaking current, which brings about neither the surge 29a nor thermal destruction, and realizing a circuit that employs the breaking current.
Moreover, a control-related problem described below confronts actions to be performed during a break derived from generation of an overcurrent. As shown in FIG. 16, the overcurrent detection means 22 detects an overcurrent condition, and the outputted overcurrent detection signal 23 is inputted to the state transition means 26b included in the diagnostic output means 26. In the state transition means 26b, a state transition is made as shown in FIG. 19. In FIG. 19, reference numeral 61a is a normal state, and reference numeral 61b is an overcurrent-sensed state.
In the normal state, an overcurrent diagnostic output 61 is set to 0. When an overcurrent condition is established, if the overcurrent detection signal 23 is outputted, the normal state is shifted to the overcurrent sensed state 61b. The overcurrent diagnostic output 61 is set to 1. Thereafter, the CPU readout control signal 32 is inputted from the CPU control means 1, and the overcurrent diagnostic output is read out. A transition is then made to the normal state. The overcurrent diagnostic output 61 is reset to 0. Simultaneously, information on the overcurrent diagnosed state is read into the CPU control means. Owing to the state transition, the CPU control means senses the overcurrent condition established in the load driving and diagnosis system, and controls the semiconductor switching circuit.
In the load driving and diagnosis system, assuming that a break occurs at timing D in FIG. 18 due to establishment of an overcurrent condition, after a predetermined pause period 25a elapses, a reset action may be automatically performed. This is a generally adopted control method. For example, when an overcurrent break occurs due to an instantaneous contact, the semiconductor switching circuit is automatically reset to the normal state in order to minimize an adverse effect on the system.
At this time, if the CPU control means reads a state-transition signal at, for example, the timing of a pulse 32b, the CPU control means can recognize the overcurrent condition at least once. However, when the CPU control means reads the state-transition signal at the timing of a pulse 32b at which the break condition still persists, since the state of the semiconductor switching circuit is returned to the normal state 61a, the CPU control means recognizes that the semiconductor switching circuit is normal.
Consequently, the CPU control means cannot recognize that the semiconductor switching circuit has entered the break condition, but controls the semiconductor switching circuit as a circuit that acts normally. Therefore, a trouble may arise in terms of control. Namely, a system malfunction may occur or the break condition caused by an overcurrent may persist while being unidentified.
An object of the present invention is to realize a load driving and diagnosis system that is insusceptible to the capacitance of a terminal capacitor or the inductance of a parasitic inductor dependent on the length of a harness and that is not adversely affected by a negative current during a break.
Another object of the present invention is to provide a load driving and diagnosis system that even when a break caused by an overcurrent persists, can accurately identify the break persistent state.